Webinars
Lincoln AI Hardware Accelerators Survey
10 June 2026 at 12:00pm ET | Virtual Event
Certain aspects of Moore’s law arguably have ended, as have a number of related laws and trends including Denard’s scaling (power density), clock frequency, core counts, instructions per clock cycle, and instructions per Joule (Koomey’s law). Taking a page from the system-on-chip (SoC) trends first seen in automotive systems and smartphones, advancements and innovations are still progressing by developing and integrating accelerators for often-used operational kernels, methods, or functions. Over the past decade, startups and established technology companies have been announcing, releasing, and deploying a wide variety of artificial intelligence accelerators. The focus of these accelerators has been on accelerating machine learning models, and the application space spans from very low power embedded voice recognition to data center scale training. Understanding the relative benefits of these technologies is of particular importance to applying AI/ML to many industry challenges and National Security domains under significant constraints such as size, weight, and power, both in embedded applications and in data centers.
This talk will share the results of an on-going, eight-year study that has been surveying AI accelerators (and accelerators, in general), including their architectures, their capabilities, and their applicability to various embedded and data center applications. The survey has grown to include well over 150 ML accelerators, and they provide a basis with which we will discuss the trends of the accelerators and what to expect in the coming years.
Guest Speaker:
Dr. Albert Reuther is a senior staff member in the Lincoln Laboratory Supercomputing Center (LLSC). He brought supercomputing to Lincoln Laboratory through the establishment of LLGrid, founded the LLSC, and oversees the LLSC Computational Science and Engineering team. As a computational engineer, he has worked with many teams within the Laboratory and beyond to develop efficient parallel and distributed algorithms to solve a wide array of computational problems. He is the co-chair of the IEEE High Performance Extreme Computing Conference and has organized numerous workshops on interactive HPC, cloud HPC, economics of HPC, and HPC security. His areas of research include interactive HPC; computer architectures for machine learning, graph analytics, and parallel signal processing; and computational engineering. Dr. Reuther earned a dual BS degree in computer and electrical engineering in 1994, an MS degree in electrical engineering in 1996, and a PhD degree in electrical and computer engineering in 2000, all from Purdue University. In 2001, he earned an MBA degree from the Collège des Ingénieurs in Paris, France, and Stuttgart, Germany.
This webinar is organized by the IEEE AI Hardware & Infrastructure Working Group.
Past Webinars
Access previous IEEE HART webinars on-demand below:
Every Bit Matters
13 May 2026 at 12:00pm ET | Virtual Event
Advances in computing hardware and system software have been a primary enabler of machine learning’s rapid progress and its impact across science, industry, and the global economy. Further gains are increasingly limited by fundamental barriers in power efficiency, memory capacity, and data movement costs. This talk will highlight some of these emerging challenges in computing for machine learning. It will also present a hardware/software co-design perspective on allowing further improvements. We will highlight recent work on datatype learning—the automated discovery and deployment of optimal numeric representations—and on techniques for optimized data encoding that minimize transfer overheads while preserving accuracy. Together, these approaches chart a path toward substantially more efficient deep learning training and inference, enabling continued scaling of model capability under practical constraints.
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Guest Speaker:
Andreas Moshovos, along with his students, has been answering the question: “What is the best possible digital computation structure/software combination to solve problem X or to run application Y?” where “best” refers to characteristics such as time to solution, power, cost, and complexity. Much of his earlier work on high-performance processor and memory system design has influenced commercial designs. His more recent work focuses on hardware/software acceleration methods for machine learning. He has been with the University of Toronto since 2000 and has taught at several institutions, including Ecole Polytechnique Fédérale de Lausanne and Northwestern University. He was the Scientific Director of the Canadian NSERC COHESA Research Network and co-founded ByteShape Inc. to commercialize machine learning model optimization technologies.
This webinar is organized by the IEEE AI Hardware & Infrastructure Working Group.
Scaling AI with Chiplet-Based Systems
17 April 2026 at 12:30pm ET | Virtual Event
In the rapidly evolving landscape of artificial intelligence, chiplets are emerging as a transformative technology, paving the way for the next generation of AI systems. Chiplets permit the integration of more processing power within a single package and allow for new connectivity solutions so that thousands of AI accelerators can work as a cohesive unit. Optical connectivity, facilitated by chiplets, offers high-speed data transmission with lower power consumption, crucial for handling the massive data loads in AI applications. The emerging chiplet ecosystem, underwritten by high-performance die-to-die interfaces, is throwing open the doors of innovation and facilitating the next wave of AI scaling.
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Guest Speaker:
Dr. Tony Chan Carusone has taught and researched integrated circuits and systems for high-speed connectivity in industry and academia for over 20 years. He has been the Chief Technology Officer of Alphawave Semi since 2022 and a faculty member at the University of Toronto since completing his Ph.D. there in 2002. He has received eleven best-paper awards at leading conferences for work on chip-to-chip and optical communication circuits, analog-to-digital conversion, and precise clock generation. He co-authored the latest editions of the classic textbooks “Analog Integrated Circuit Design” and “Microelectronic Circuits,” the best-selling engineering textbook ever. He is a Fellow of the IEEE.
This webinar is organized by the IEEE AI Hardware & Infrastructure Working Group.